The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by their inclusion in this section.
As transistor sizes continue to shrink, this may result in more complex manufacturing processes required to create a system on-chip (SOC), and may result in long manufacturing process hold times. To overcome these manufacturing difficulties, replicating multiple dies on the same package to create a SOC has been used to reduce the overall die size.